The present invention relates to digital-to-analog converters (DACs) that provide improved linearity, low total switch area, and greater insensitivity to parasitic resistances than conventional voltage-mode DACs. In particular, it relates to such DACs having separate force and sense switches for each independently switched resistor within the DAC.
An integrated voltage-mode digital to analog converter consists of a network of resistors and switches. One node of the network is the output voltage and another two nodes are reference voltages. The analogue output voltage is a voltage that lies somewhere between the two reference voltages as determined by a digital input code. Common designs for high accuracy voltage-mode DACs include binary weighted R2R architectures and segmented architectures that include equally weighted segments or are hybrids between the equally segmented architecture and the R2R architecture. These architectures are discussed in Razavi, Principles of Data Conversion System Design, Wiley-IEEE Press (1994). Although these designs vary in architecture, each design provides a plurality of switchable cells that are activated based on the digital code input to the DAC. The activated cells contribute to an analog voltage generated at the DACs output. Each cell's contribution is determined, at least, in part based on the resistance of the cell itself and any coupling resistance that extends between the cell and the output terminal.
In integrated circuits, resistors are often manufactured from a precision thin-film process, while the switches typically are CMOS transistors. It is normal that the resistors are all quite similar in value and size, while the CMOS switches are scaled in some ratio to reduce their contribution to integral non-linearity (INL) error of the DAC. However, the CMOS transistors are still not ideal, for several reasons. In particular, they have some resistance associated with them, which is not linear. Voltage drops across this resistance contribute to the INL error. Moreover, the resistance associated with these CMOS switches varies according to the voltage they operate at and, since there are switches to two different reference voltages, it can reasonably be expected that these will have different resistances at different switch settings. Although some attempts have been made to equalize these switch resistances to minimize this source of INL error, generally some residual error persists due to the accuracy of the method itself. CMOS transistors also have leakage currents to their back-gates, particularly at high temperatures, which can provide a further source of INL error.
The problems associated with CMOS transistors become a more significant design concern for higher accuracy, higher voltage DACs (for example, a 16 bit DAC operable at voltages in excess of 5V). The error contribution of CMOS switches is larger than the maximum error permitted. Although larger CMOS transistor switches can withstand higher voltages as compared smaller CMOS switches for the same area, they provide higher resistance which increases the voltage drops across them and the INL contribution. Higher voltage switches also have more leakage.
Conventionally, to provide a voltage-mode DAC that is very accurate, circuit designers use large CMOS switches. Larger switches generally have lower switch resistance, which decreases associated INL error. However, the use of large switches has consequences, such as: requiring larger silicon die area, increasing parasitic capacitance and increasing leakage current at high temperature (another source of INL error), increasing transition currents as new digital codes are loaded into the DAC, and layout/routing problems due to different lengths of interconnect among DAC resistors. Also larger switches require more silicon area, adding cost, and the larger physical size makes miniaturization more difficult
Accordingly, there is a need in the art to avoid use of large switches in a voltage-mode DAC.